12.2 A CMOS-compatible Fabrication Process for Scaled Self-Aligned InGaAs MOSFETs

We have developed a scalable gate-last process to fabricate planar self-aligned InGaAs Quantum-well (QW) MOSFETs that relies on extensive use of dry recess. The fabrication sequence yields precise control of all critical transistor dimensions, in particular, the length and thickness of the channel and the access regions. The process involves a combination of anisotropic and isotropic F-based dry etching of refractory metal ohmic contacts that are formed early in the process. Anisotropic Cl-based dry etching is used to recess the In-based III-V cap material. A digital etch technique that achieves a thickness control down to ~1 nm is used to trim the channel to its final thickness. We have demonstrated Lg=20 nm MOSFETs with 15 nm contact-gate separation and good electrical characteristics. A device design optimized for transport exhibits a record transconductance of 3.1 mS/m.